1. Technical Field
Generally, the present disclosure relates to the field of semiconductor based devices, such as devices including thin film transistors (TFT) that are formed on the basis of organic semiconductor materials.
2. Description of the Related Art
Immense progress has been made in the field of semiconductor production techniques by steadily reducing the critical dimensions of circuit elements, such as transistors, in integrated circuits. For example, critical dimensions of 30 nm and less have been implemented in highly complex logic circuitry and memory devices, thereby achieving high packing density. Consequently, more and more functions may be integrated into a single semiconductor chip, thereby providing the possibility of forming entire systems on a chip so that highly complex electronic circuits may be implemented on the basis of a common manufacturing process. Complex integrated circuits that are produced on the basis of volume production techniques are mainly based on CMOS technology using silicon as semiconductor base material due to the many advantages of silicon in terms of availability, costs, well-established production technology and the like. The significant advance of silicon-based products can mostly be attributed to the remarkable reduction of critical dimensions, thereby allowing the production of an ever increasing number of integrated circuits on a single wafer. Nevertheless the cost of well-established silicon-based production techniques per unit area are still high and may not be compatible with economic demands when considering electronic devices used for large area applications. For example, flexible cost efficient displays, RFID tags for many types of products, and the like represent typical applications, in which low production costs rather than extremely reduced critical dimensions substantially determine economic success of a corresponding technology.
In this respect organic thin-film transistors and integrated circuits fabricated on the basis of such organic TFTs have gained in importance over the recent years due to their capability of being produced on the basis of less demanding production techniques compared with well-established semiconductor fabrication technologies. Basically organic TFTs are encountered in four different types of structures, each of which may have advantages and disadvantages in terms of production process related issues and/or performance. One type of transistor structure is the bottom gate and top contact type, in which a gate electrode is formed on an appropriate substrate, followed by a dielectric material that serves as gate dielectric material and also encapsulates the gate electrode. Thereafter, the organic semiconductor material is provided, followed by the source and drain electrodes. Consequently, by applying cost efficient deposition techniques for the various materials, for instance for the organic semiconductor material and the source and drain material, for instance provided on the basis of a metal, such as gold, the deposition process for the source and drain electrodes may have to be carefully selected with respect to the organic semiconductor material. For example, one frequently used deposition technique is inkjet printing, which typically specifies that the conductive material for the electrodes to be printed on the basis of a solvent. Hence, this solvent has to be selected so as to not substantially interfere with the previously formed organic semiconductor material, thereby significantly limiting the number of available conductive inks that are available for inkjet printing. Furthermore, organic semiconductor materials may frequently have a hydrophobic surface, which may reduce adhesion of the source and drain materials, thereby reducing overall reliability. Furthermore, a top gate and bottom contact structure may be used, which is similar to well-established silicon-based planar transistor architectures, in which source and drain electrodes or regions are formed above the substrate, followed by the organic semiconductor material. Thereafter, an insulating material is provided, followed by the gate electrode. In this type of structure the organic semiconductor material is deposited as the second layer, so that subsequent process steps, such as printing and curing of subsequent materials may result in a deterioration of the semiconductor material. Therefore, the selection of materials and solvents, when considering inkjet printing, is extremely challenging.
For this reason, in many approaches the organic semiconductor material is provided as a last layer of the basic transistor configuration. A widely used structure in this respect is the back gate and bottom contact type, in which frequently a heavily doped silicon substrate is used as a carrier material, while at the same time serving as the back gate electrode. A dielectric material is formed on the gate electrode layer, for instance in the form of a thermally grown oxide. The source and drain electrodes are typically deposited by evaporation of an appropriate metal, such as gold, which is patterned by a lift-off method. The organic semiconductor material is frequently spin coated or printed, for instance inkjet printed, so as to complete the basic transistor structure. Due to the full overlap between the source and drain electrodes and the back gate a moderately high parasitic capacitance is encountered, thereby significantly reducing overall transistor performance. On the other hand, this structure may be favorable for printing processes, since the semiconductor material is provided as the last layer, thereby avoiding any solvent attack that may occur in other configurations, when incompatible solvents have to be used for printing another device layer, such as a metal layer, onto the semiconductor material.
In order to address the significant parasitic capacitance of the back gate and bottom contact transistor structure, previously described, a further transistor configuration has been proposed, in which the sequence of different material layers is maintained, wherein, however, a patterned gate electrode is provided. This configuration is referred to as a bottom gate and bottom contact structure. The patterned gate electrode may be contacted on the basis of an appropriate bottom contact regime, while nevertheless reducing the parasitic overlap between the gate electrode and the drain and source electrodes.
FIG. 1A schematically illustrates a cross-sectional view of an organic transistor structure 150 according to a bottom gate bottom contact (BGBC) structure type. As shown, the transistor structure 150 comprises a substrate 101, which may represent any appropriate carrier material, such as a semiconductor material, glass, plastic, and the like, which may even be flexible, depending on the type of application, for which an electronic device including the transistor structure 150 is to be used. A patterned gate electrode 151 comprised of an appropriate metal, such as aluminum, is formed on the substrate 101 and has appropriate lateral dimensions so as to comply with the overall layout of the transistor structure 150. A dielectric material 152, such as an organic dielectric, and the like is formed above the gate electrode 151, thereby serving as a gate dielectric material. Moreover, the dielectric material 152 may also be provided laterally adjacent to the gate electrode 151 in order to electrically insulate and confine the gate electrode 151. Drain and source electrodes 153/154 are formed on the gate dielectric material 152 with a desired extension along a transistor width direction, i.e., a direction perpendicular to the drawing plane of FIG. 1A, while the transistor length is determined by the lateral distance of the drain and source electrodes 153/154. Moreover, an organic semiconductor material 155, such as pentacene, and the like, is formed above and between the drain and source electrodes 153/154. As is evident from FIG. 1A, by appropriately dimensioning the gate electrode 151 and the drain and source electrodes 153/154 a desired channel length may be determined without inducing undue parasitic capacitance, since the overlap of the gate electrode 151 with the drain and source electrodes 153/154 may be adjusted in terms of transistor performance by appropriately adjusting the lateral dimensions of the gate electrode 151.
Since the specifications with respect to critical dimensions of organic thin film transistors are significantly less demanding compared to cutting edge bulk silicon technology, the patterning of the various material layers is frequently achieved on the basis of physical vapor deposition using a shadow mask, which in turn may result in reduced overall production yield due to the moderately complex process and the interference of the shadow mask with the deposited material upon removing the mask. In other approaches, as discussed above, the deposition may be accomplished on the basis of spin coating and/or dipping processes, in which the actual materials are deposited in combination with an appropriate solvent, thereby requiring subsequent patterning, for instance by photolithography, imprint techniques and the like. Basically blanket-deposition techniques in combination with lithography processes are precise and well-established methods for patterning various material layers, however, these techniques significantly contribute to overall production costs, in particular for organic semiconductor devices, in which lithography cost per unit area are moderately high due to significantly reduced device density compared to cutting edge silicon technology. Therefore, other deposition techniques, such as inkjet printing, have been proposed in order to form patterned material layers by using solvent-based conductive and insulating materials. These printing techniques also typically are followed by further processing, such as to provide high degree of compatibility of the various solvents in order to avoid significant material deterioration caused by the subsequent printing and treatment of the solvent of a subsequent material layer.
Based on the above described process technologies a plurality of types of electronic devices including organic TFTs have been produced so as to address the increasing demand for cost efficient electronic products. In earlier approaches exclusively p-type TFTs have been used due to the less critical availability of p-type organic semiconductor materials of moderate charge carrier mobility and a sufficient stability, thereby allowing the fabrication of active displays, sensors and the like. For example, pentacene in combination with gold electrodes, which match the highest occupied molecular orbital (HOMO)-lowest unoccupied molecular orbital (LUMO) regime of the pentacene, results in appropriate transistor performance. On the other hand, there are significant advantages involved in implementing p-type transistors and also n-type transistors when producing complex electronic circuits. For example, in standard inorganic semiconductor devices CMOS circuits exhibit a significantly reduced power consumption due to the fact that power is mainly dissipated during transistor switching operations, while extremely low power consumption occurs in the steady-state of the transistors. That is, CMOS circuits consume significantly less power compared to n-MOS or p-MOS devices. Although it is believed that in organic circuits power dissipation is dominated by leakage currents, nevertheless significant effort has been made in order to design complementary circuits on the basis of organic TFTs. Furthermore, advantages, such as reduced design complexity, greater speed, superior immunity to noise effects and reduced sensitivity to transistor characteristics, as are encountered in standard silicon CMOS technology, may also represent important improvements in organic circuits when based on complementary transistors. Therefore, extensive research has been done in recent years in order to provide n-type organic semiconductor materials that exhibit sufficient carrier mobility and stability during processing and after finishing the electronic product. For example, hexadecafluorocopper phthalocyanine (F16CuPc) or materials from the oligothiophene, fullerene and rylene imide groups have been identified as appropriate n-type materials.
Upon forming organic circuits on the basis of complementary TFTs, however, the deposition of two different types of organic semiconductor materials may result in additional process complexity, for instance requiring additional photolithography and patterning processes so as to provide the two different semiconductor materials with appropriate lateral position, size and shape. When avoiding lithography techniques, for instance by using a spatially selective deposition technique on the basis of a shadow mask, a further reduction in overall production yield may be observed due to the interference of the additional shadow mask with the sensitive material deposited.
Although recent research has revealed that the same type of organic semiconductor material may exhibit different conductivity types in combination with different metal electrodes and/or dielectric materials provided at the interface to the organic semiconductor material, nevertheless also in this case additional significant complexity is associated with the fabrication of CMOS devices. For example, sophisticated gate dielectric materials with reduced thickness and specified molecular structure may have to be used in order to appropriately control the conductivity type at the interface to the organic semiconductor material in order to adjust the desired transistor behavior. For example, frequently so-called self assembling monolayers (SMAs) may be used as a gate dielectric in order to appropriately adjust interface characteristics. On the other hand, although desirable with respect to enhanced controllability of the channel region, a dielectric material of reduced thickness may even further contribute to increased leakage currents, which may represent a considerable contribution to the overall power losses of organic circuits, as already discussed above.
In view of the difficulties associated with the formation of organic CMOS devices several approaches have been proposed in order to address at least some of the above-identified problems. For example, in “Organic Pseudo-CMOS Circuits for Low-Voltage Large-Gain High-Speed operation”, IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 10, October 2011, organic TFTs are described, which are appropriately connected in order to implement a CMOS-like circuit so as to gain at least some of the advantages of a CMOS design, while circumventing some of the problems associated with the provision of two types of organic semiconductor materials.
FIG. 1B schematically illustrates a cross-sectional view of a transistor structure 150, in which a gate electrode 151 comprised of aluminum is formed on a substrate 101. A gate dielectric material includes a first dielectric layer 152A made of aluminum oxide and a second dielectric layer 152B comprised of an organic material of self aligned monolayers (SAM) with a reduced thickness of approximately 2 nm. Then, an organic semiconductor material 155 in the form of DNTT (dinaphto[2,3-b:2′,3′-f]thieno[3,2-b]thiophene) is provided with a thickness of approximately 30 nm, followed by drain and source electrodes 153/154 made of gold. The organic TFTs described in this document have been manufactured by vacuum evaporation and low-temperature solution processes, wherein the vacuum evaporation processes have been performed on the basis of respective shadow masks. The gate dielectric material 152B may be provided on the basis of a complex and long solution process.
Although the transistor shown in this document provides for moderately high mobility and thus switching speed, nevertheless reduced device density is associated with the pseudo-CMOS design, since four TFTs 150 are used to implement an inverter structure, which in CMOS design is achieved on the basis of one p-type transistor and one n-type transistor.
In view of the situation described above there is an increasing demand for organic circuits with superior performance with respect to operating characteristics, which may be fabricated on the basis of process technologies that provide for superior production yield, such as photolithography techniques, compatibility with industrial standards for volume production, yet allowing a very cost effective manufacturing flow in order to meet economic constraints for a wider field of electronic products.